In various fields, such as data communications and data storage, the data is protected by applying Error Correction Coding (ECC). ECC typically involves calculating redundancy or parity bits that can be used for detecting and correcting corrupted data. Some types of error correction codes, such as Generalized Low-Density Parity-Check (GLDPC) codes, can be defined using a parity-check matrix. Processing GLDPC codes typically involves calculating a syndrome for each of the component codes. The syndromes are then used for finding error locations in decoding, and for generating redundancy information in encoding.
Methods for syndrome calculation are known in the art. For example, U.S. Pat. No. 4,030,067, whose disclosure is incorporated herein by reference, describes an apparatus for directly decoding and correcting double-bit random errors per word and for detecting triple-bit errors per word. Said apparatus comprises a syndrome calculator which operates upon code words received from memory and generates syndromes. The syndromes are operated upon and translated by a mapping device which generates pointers identifying the bits which are in error.
In some applications, the GLDPC encoder or decoder needs to be implemented in hardware. Hardware and firmware implementations of a component decoder such as a BCH decoder are known in the art. For example, U.S. Pat. No. 8,381,082, whose disclosure is incorporated herein by reference, describes power-saving and area-efficient BCH coding systems that employ hybrid decoder architectures. The BCH decoder architectures comprise both special-purpose hardware and firmware. In particular, the error correction capabilities of the BCH decoders provided herein are split between a hardware component designed to correct a single error and a firmware component designed to correct the remaining errors.